1. Field of the Invention
This invention relates generally to semiconductor memory circuits and more particularly to an improved insulated-gate-field-effect-transistor (IGFET) sense amplifier suitable for use within a random access IGFET memory integrated circuit.
2. Description of the Prior Art
Latching type sense amplifiers have been used in the past both for static and dynamic random access IGFET memory circuits. For example, an application of a latching sense amplifier within a static IGFET RAM is shown in Schlageter et al., "Two 4K Static 5-V RAMs", IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 5, October 1976, at page 602. An application of a latching sense amplifier within a dynamic IGFET RAM is shown in Ahlquist et al., "A 16,384-Bit Dynamic RAM", by Ahlquist et al., IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 5, October 1976, at page 570. It has been common to connect the bit lines, leading from the memory cell to the sense amplifier, to the switching nodes of the cross-coupled circuit within the sense amplifier in order to latch the sense amplifier in the proper state. One of the disadvantages of this technique is that the capacitance associated with the switching nodes of the cross-coupled circuit tends to slow the rate at which the bit line voltage can be switched by the memory cell prior to latching the sense amplifier. In addition, the sense amplifier latch circuit can not be enabled until the voltages at the switching nodes of the cross-coupled circuit have been pulled apart from one another. The overall effect, then, is to delay the enabling of the latching sense amplifier a relatively long time beyond the selection of the memory cell.